# coscope ### The AI copilot for hardware bring-up & debug. It reads your schematic, firmware, and bench instruments at the same time, so a new board comes up in hours instead of weeks. *Berlin · Angel round · 2026* --- ## 01 - The problem: bringing up a new circuit board is still a manual, undocumented guessing game. When a freshly assembled board hits the bench, a senior engineer ($150 to $300/hr, fully loaded) has to reconcile three things in their head: - the **schematic & BOM** (what it *should* do) - the **firmware** (what it's *trying* to do) - the **bench instruments** (what it's *actually* doing: scope, logic analyser, DMM, power supply) No tool holds all three at once. So the engineer works it out by hand, and the only record survives like this: > "9 out of 10 times, someone snaps a pic with their phone." > - practising EE, Hackaday (2024) **The three costs:** 1. **Time.** Bring-up is the most expensive bench time you'll buy, and it gates every stage of development. 2. **Knowledge loss.** "Single source of truth is the biggest, biggest problem in embedded/hardware products." (Head of Embedded, araCreate). Documentation collapses the moment a deadline appears, because "more time never arrives." 3. **Handoff tax.** A board handed to another engineer, or picked up again after three weeks, has to be understood from scratch. --- ## 02 - Why now: three things became true in the last 18 months. The capability and the appetite arrived at once. 1. **AI can finally reason over messy hardware data.** LLMs can now read datasheets, schematics, and instrument traces together. Proof it works: an Amazon EE lead built an internal design-checker and injected dozens of errors. Properly guided, a frontier model caught **100%**. 2. **AI can now operate the bench, not just read it.** Agentic tool use almost always points at software tools (MCP servers, APIs). We point it at *physical instruments* (scope, logic analyser, power supply), driven in a loop against the live PCB with captures read back. 3. **Engineers actually want AI in their workflow now.** Eighteen months ago, using AI at work was a novelty. Now it's expected, and teams are actively hunting for the next job to hand it. The appetite, and the budget behind it, arrived before anyone built the tool that fits the bench. > The plumbing exists, the AI is good enough, and nobody has wired them together for the engineer at the bench. --- ## 03 - The solution: the one place that holds your design *and* your measurements, and reasons across both. You connect your project (schematic / BOM / firmware) and your bench. Then the agent does what a senior EE does, only faster: - **Design-aware debugging.** *"This rail should be 3.3 V ±5% per your schematic, but the DMM reads 3.8 V, so check R47 and C23."* It knows the intent, so it knows when reality disagrees. - **Cross-instrument correlation.** Scope traces + logic-analyser decodes + DMM + PSU readings, lined up against the design and firmware state, automatically, instead of you eyeballing four screens. - **A bring-up journal that writes itself.** Every probe, reading, and conclusion captured as a searchable, time-stamped record. That record is your handoff doc and your compliance artifact, for free. It runs alongside Altium, KiCad and Cadence rather than replacing them. We read your design files, so you never switch CAD tools. **Why this is the right shape:** - **Reliability is verifiable.** "AI that lays out your board" is judged on aesthetics. Our output is checked against an instrument reading, so right or wrong is measurable. - **No rip-and-replace.** Zero switching cost is the entire adoption strategy. - **Cross-vendor by design.** Keysight, Tektronix, Siglent, Rigol, Saleae: one agent across all of them. --- ## 04 - Founder-market fit: for 15 years, I've either been at this bench myself or leading the teams doing the work. **Tom Elliot - Founder** - **Built the industry's first all-day, wrist-worn heart-rate sensor at Fitbit**, the lowest-power PPG sensor of its time. I took it from R&D to the factory line in the Fitbit Surge, and was Sensor Systems Lead for the Fitbit Ionic. I've lived hundreds of hours of the bring-up and debug pain this solves. - **Led hardware teams from IoT to industrial products:** Head of Hardware Engineering at INFARM, Head of Engineering at Senic. Coached teams to ship reliably. I know how hardware orgs work, and how they buy. - **Bootstrapped B2B SaaS for 3 years**, with a consistent income stream the last 18 months. I've honed product, sales, and software-engineering chops the hard way. **Why me, specifically:** - **Domain credibility customers trust on day one.** I've sat where my users sit. They open the door because I speak their language, not because I'm pitching them. - **I run the company the way the product thinks, AI-native by design.** Agents already do the work a team would: customer-discovery synthesis, research, ops, and engineering, all orchestrated through OpenClaw, Claude Code, and whatever comes next. Smallest possible team, compute over headcount. --- ## 05 - Validation / traction: the pain is real, the buyers are senior, and the pull is already there. **From the bench (customer discovery):** - A Berlin embedded lead (araCreate) runs board bring-up "purely manual, with an oscilloscope" and keeps a "bugs and fixes" log by hand. As he puts it: "the most crucial part is how I fixed it; the issue recurs after six months and I can't remember." He has already built his own driver loops to pull readings off his bench instruments (Rigol and others) for one-off projects, and is "trying to make it work generically." He is building coscope himself, without us. - An EE at a 7-EE audio hardware team (Teufel, ~12 products/yr) takes notes on "everything" during bring-up, and, unprompted, described our exact core loop: he wants AI to review his logic-analyser I²C streams and work out where it went wrong. In his board-spin tracker, most of the issues originate in debug and bring-up. **Proof the approach works:** - The same Amazon signal from Why Now, now with money behind it: its EE lead won VP-level budget to build the design-checker in-house. Big companies are validating the thesis with their own money. --- ## 06 - Market: we sell time back to the most expensive engineers in the building. **Bottom-up logic (the number that matters):** - A senior EE costs **$150 to $300/hr** fully loaded. - Bring-up and debug is a **gating, weeks-long** step on every board revision; the early revs alone run **20 to 40 hours each**. - Across a year that's a few hundred senior-EE hours, or **$25k to $90k of one engineer's time**, in a phase with no dedicated tool. So the wedge ACV is a per-seat number anchored to that labour, not to a CAD licence. **Beachhead → expansion:** - **Beachhead:** well-funded **robotics & hardware startups** (Foundation, Bedrock, Mytra, et al.) and **product teams / consultancies** shipping in a hurry. They feel bring-up pain weekly and move fast on tools. - **Expand:** the broader installed base. The EDA tools market alone is about **$10B/yr** (Altium plus Cadence), on top of a roughly **$40B** engineering-tools market. Not a TAM claim, just the direction once the wedge lands. **A growing market:** AI means more new hardware products, built faster by leaner teams. More boards to bring up is our tailwind. --- ## 07 - Competition & differentiation: the AI-EDA wave is real, and it's all aimed at *designing* the board. Nobody is at the bench *after* it's built. | Where the money's going | Players (funding) | What they do | Why it's not us | |---|---|---|---| | **Prompt-to-hardware** (for beginners) | Schematik ($4.6M pre-seed, Lightspeed-led), Atech ($800K pre-seed, Sequoia · a16z · Lovable) | Plain-English idea → code, wiring, modules, first prototype | Built for people who "don't know what a resistor is." It's idea to first prototype, not bring-up or debug of a real board. | | Physics-driven **layout** | Quilter ($40M; real enterprise traction) | Autonomous PCB placement & routing | Pre-fabrication design. Explicitly not schematic gen, not bring-up. | | Browser **AI copilots** | Flux (~$49M), Allspice, Circuit Mind | In-browser design + chat copilot | Flux's "debug" feature is pasting a scope screenshot into chat. It isn't instrument-integrated. | | **Code-as-source** EDA | JITX, atopile, tscircuit, Diode | Define hardware in code | A new design front-end; doesn't touch the bench. | | Incumbents | Cadence (Allegro X AI), Siemens, Altium | AI folded into 30-yr-old suites | System-level design + simulation; not the cross-vendor bench. | **The bring-up and debug wedge is wide open.** A closed-loop, design-aware, cross-instrument agent is the one product none of them is building. **Our defensibility:** - **Cross-vendor and design-aware from day one,** the one thing single-instrument copilots structurally can't be. - **A proprietary data flywheel:** every bring-up session pairs design intent with real measured outcomes. That's training data nobody else is collecting. **The objection to pre-empt:** *"Won't the scope vendors (Keysight, R&S, Tektronix) just add their own AI?"* They will. And it will be single-instrument and brand-locked, while real benches are mixed-vendor. The opening is exactly the place a Keysight copilot can't go: across all your instruments, tied to your design. --- ## 08 - Business model: start as per-seat SaaS. Grow into the hardware the software runs on. **Today: software, priced against the labour we save.** - **Model:** per-seat subscription for each engineer at the bench. Land with the lead EE, expand across the hardware team. - **Pricing logic:** we save a $150 to $300/hr engineer hours on every board they bring up. A four-figure annual seat is a rounding error against that. - **Reference point:** hardware-in-the-loop tools already sell at ~$5k/year to companies (per discovery). Buyers pay real money for this category. - **Why it works:** pure software on top of existing CAD and bench gear (no hardware COGS), paid out of the labour budget, the largest and least-defended budget in the building. **The arc: software opens the market, hardware is the long-term moat.** > As AI drives the cost of software toward zero, code stops being defensible. The durable advantage is the bench itself: our own debug & capture hardware, designed around the agent. When every competitor can ship the software, the hardware is what drives adoption and retention. - **The moat:** a closed software-defined-instrument loop an incumbent scope vendor can't copy without rebuilding their software, and a SaaS competitor can't copy without building hardware. --- ## 09 - The ask: raising a $250k angel round on a rolling SAFE to prove the wedge with paying design partners. **The round:** - **Target:** $250k angel round - **Instrument:** Rolling SAFE (single cap, uncapped tranches), founder-friendly and fast to close. We close investors as they commit instead of waiting to fill a whole round. That keeps momentum and lets a lead set the price. - **Stage:** first investor conversations. The investment window is mid-July to mid-August. - **Why $250k goes far:** we're AI-native inside and out, compute over headcount. Tokens are the largest cost, not salaries, so this round behaves like a bigger one. And token costs keep falling fast, roughly 10× a year. **What it buys: 12 months to a priced seed.** 1. **Ship the MVP** that closes the schematic ↔ firmware ↔ instrument loop on real benches. 2. **Get 3+ design partners paying.** A cheque is the proof the pain is real and engagement is genuine. 3. **Prove the wedge segment** (funded robotics/aerospace teams). 4. **Automate internal ops.** **What I want from you, beyond the cheque:** - Intros to hardware teams (robotics, aerospace, consumer EE) for design partners. - Conviction that hardware is about to accelerate the way software did, and that coscope is the tooling layer for it.